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Application-Specific Memory Access by Prefetching via High Level Synthesis

Authors:
İsmail San
Atakan Doğan
Kemal Ebcioğlu

Keywords: High level synthesis; Memory access time; Off-chip memory latency; Application-specific memory hierarchy.

Abstract:
High Level Synthesis (HLS) allows an automatic translation from high level C/C++ descriptions into Register Transfer Level (RTL) hardware designs. HLS enables to design at a high level of abstraction that offers one to focus on high level concepts within less amount of design time. Once a specific data intensive application is considered to be accelerated in hardware, its memory access pattern must be exploited for higher performance. Most of the time, an application suffers from a high amount of memory access latencies. To reduce the memory access latencies, we use widely known prefetching technique to mask the latencies. In this paper, we enabled a data prefetching scheme specified at the C/C++ descriptions level via Vivado HLS, which overlaps double-buffered prefetching and computation.

Pages: 30 to 35

Copyright: Copyright (c) IARIA, 2018

Publication date: July 22, 2018

Published in: conference

ISSN: 2519-8459

ISBN: 978-1-61208-658-3

Location: Barcelona, Spain

Dates: from July 22, 2018 to July 26, 2018