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4T Loadless SRAMs for Low Power FPGA LUT Optimization

Authors:
Karol Niewiadomski
Carsten Gremzow
Dietmar Tutsch

Keywords: FPGA; LUT architecture; SRAM cell optimization; low-power; leakage-current reduction; power reduction measures

Abstract:
The adaptiveness of Field Programmable Gate Arrays (FPGAs) is a key aspect in many mobile applications. Modern vehicles contain up to 100 ”Electronic Control Units” (ECUs) in order to implement all necessary functions for autonomous driving. Due to the limited power resources of mobile applications, an appropriate implementation of power reduction measures is crucial for achieving an acceptable amount of power savings. Commercial Electronic Design Automation (EDA) tools support the designers to implement low-power circuits on architectural level. However, effective power reduction mechanisms have to be applied to the backbone of each FPGA: the look-up table (LUT). In this paper, we describe the implementation and comparison of various LUTs based on different Static Random Access Memory (SRAM) cells. All SRAM cells have been analyzed in order to evaluate feasible modifications for the sake of lowering leakage currents and modified in order to minimize static and dynamic power consumption. Followed by a comparison of different LUT implementations based on the optimized SRAM cell designs, we derive further optimization approaches to achieve effective power savings for the usage in environments like vehicles, smartphones, etc. with limited power.

Pages: 1 to 7

Copyright: Copyright (c) IARIA, 2017

Publication date: February 19, 2017

Published in: conference

ISSN: 2308-4146

ISBN: 978-1-61208-532-6

Location: Athens, Greece

Dates: from February 19, 2017 to February 23, 2017