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Low Power Tristate Buffer for Mobile Applications

Authors:
Karol Niewiadomski
Dietmar Tutsch

Keywords: Tristate buffer; GPIO; Power reduction; Leakage suppression; Energy efficiency

Abstract:
The adaptiveness of integrated electronics is a key feature in current and future mobile applications. Despite the continuous improvement of battery capacity, reconfiguration capabilities of integrated electronics are an inevitable step to cover the rising demand for processing power. Without any further adjustments for efficiency, power consumption becomes a limiting factor for runtime performance. Field Programmable Gate Arrays (FPGA) provide suitable configuration capabilities, but lack of efficient power saving design measures. To overcome this challenge, different approaches were proposed in recent research activities. A substantial contributor to battery load are General Purpose Input Output (GPIO) circuits, which serve the purpose of connectivity. In this paper, we present a modified tristate buffer, which is a key component in a typical GPIO design. Modifications for active power reduction and standby leakage current suppression are applied at circuit level to achieve a better energy efficiency. This new tristate buffer design is compared to already existing designs.

Pages: 9 to 14

Copyright: Copyright (c) IARIA, 2018

Publication date: February 18, 2018

Published in: conference

ISSN: 2308-4146

ISBN: 978-1-61208-610-1

Location: Barcelona, Spain

Dates: from February 18, 2018 to February 22, 2018