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MORUS-PRNG: a Hardware Accelerator Based on the MORUS Cipher and the IXIAM Framework

Authors:
Alessio Medaglini
Mirco Mannino
Biagio Peccerillo
Sandro Bartolini

Keywords: cryptographic accelerators, hardware accelerators, simulation, ciphers, pseudorandom sequences.

Abstract:
High-quality Pseudo-Random Number Generator (PRNG) is crucial in many applications that span a variety of fields. A common way to implement PRNGs is by exploiting an underlying secure ciphering algorithm, since its ciphertexts have statistical properties very close to those of a random sequence. Depending on the nature of the application requiring random values and its constraints, the ability of such a PRNG to generate numbers with high throughput and/or limited latency can be paramount. In recent years, programmers and researchers have been relying on hardware accelerators for many computation tasks where performance matter, moving progressively away from classic all-CPU software solutions. Ciphering algorithms and PRNGs have benefited from this tendency as well. In this paper, we propose a PRNG based on the MORUS cipher as an integrated accelerator that can be connected to CPU cores through the IXIAM layer, which allows a fast host-accelerator communication with RISC-V instructions. We measure performance in CPU cycles per number in the gem5 architecture simulator, and compare our implementation against plain software solutions provided by the C++ standard library. We show that our implementation outperforms them, with speedups above 2×.

Pages: 1 to 7

Copyright: Copyright (c) IARIA, 2024

Publication date: September 29, 2024

Published in: conference

ISSN: 2308-4499

ISBN: 978-1-68558-184-8

Location: Venice, Italy

Dates: from September 29, 2024 to October 3, 2024