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Design and Implementation of Simulation Engine for Very High-Rate Communication over Power Grid
Authors:
Sungsoo Choi
Hui-Myoung Oh
Keywords: very high-rate power line communications; advanced metering infrastructure; smart grid; FPGA; ISO/IEC 12139-1
Abstract:
This paper discusses the design of an engine to simulate a Very high-rate Power Line Communication (VPLC) infrastructure that handles up to a rate of 400 Mbps. The simulation engine complies with the ISO/IEC 12139-1 standard for power line communication protocols. The engine can be used as one of the access network elements deployed in the advanced metering infrastructure in a smart grid. We first propose a feasible system model of VPLC in line with the design goals with pre-simulations, i.e., an event-driven simulation and a timing-driven simulation. Next, we design a semiconductor Intellectual Property (IP) core, focusing on the implementation of two main functional IP cores of the entire system: a fast Fourier transform for modulation/demodulation and a low-density parity-check encoder/decoder for forward-error correction. Finally, the designed VPLC based on the main functional IP cores is implemented on an available FPGA chipset, targeting the Virtex-6 xc6vlx240T.
Pages: 19 to 25
Copyright: Copyright (c) IARIA, 2014
Publication date: July 20, 2014
Published in: conference
ISSN: 2308-4030
ISBN: 978-1-61208-360-5
Location: Paris, France
Dates: from July 20, 2014 to July 24, 2014