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Area and Speed Efficient Layout Design of Shift Registers using Nanometer Technology

Authors:
Rajesh Mehra
Priya Kaushal
Ayushi Gagneja

Keywords: CMOS; Flip Flop; Shift Register; SISO; SIPO; VLSI

Abstract:
The paper presents an area and speed efficient CMOS layout design of shift register on 180 nanometer (nm) technology. The proposed shift register is designed using Serial In Serial Out (SISO) and Serial In Parallel Out (SIPO) techniques. Shift registers are commonly used in large number of sequential circuits and processors for temporary storage of data. The area and speed of developed layout designs are improved by optimized placement and routing for layout. The schematic and layout of both designs are simulated and analyzed using Cadence software. It can be observed from simulated results that the delay of SISO register is 0.97 ns and the delay of SIPO register is 0.71 ns. The SISO register shows 78.6% improvement in delay and SIPO register shows 27.46 % improvement in delay. The silicon area consumption of SISO register is 140.6 nm x 129.49 nm and SIPO register is 130.98 nm x 85.91 nm to provide cost effective solution for Very Large Scale Integration (VLSI) applications.

Pages: 58 to 62

Copyright: Copyright (c) IARIA, 2017

Publication date: March 19, 2017

Published in: conference

ISSN: 2519-836X

ISBN: 978-1-61208-543-2

Location: Nice, France

Dates: from March 19, 2017 to March 23, 2017