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Efficient Implementations of Radix-4 Parallel-Prefix Trees

Authors:
Stefania Perri
Pasquale Corsonello

Keywords: Adders; VLSI circuits; parallel-prefix trees

Abstract:
This paper presents novel dynamic circuits purpose-designed to realize parallel-prefix adder trees with computational delay and power consumption lower than the conventional domino logic implementations. The proposed circuits increase speed by reducing the complexity of the pull-down networks of each dynamic gate; and save power by reducing the number of dynamic stages within the overall structure of the generic parallel-prefix tree. When the ST 45nm 1V CMOS technology is used, 32-bit radix-4 Brent-Kung, Han-Carlson and Ladner-Fischer trees designed as proposed here achieve, respectively, a computational delay of 148ps, 129.6ps and 117.2ps; dissipate 194fJ, 240fJ and 209fJ; and shows a silicon area requirement of 160um2, 190um2 and 170um2.

Pages: 1 to 5

Copyright: Copyright (c) IARIA, 2011

Publication date: August 21, 2011

Published in: conference

ISSN: 2308-426X

ISBN: 978-1-61208-150-2

Location: Nice/Saint Laurent du Var, France

Dates: from August 21, 2011 to August 27, 2011