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Comparison of Three Impedance Analysers Implemented on FPGA Circuits

Authors:
Abdulrahman Hamed
Etienne Tisserand
Patrick Schweitzer
Yves Berviller

Keywords: - electrical impedance spectroscopy; piezoelectric transducer; FPGA; DDS; Hardware In the Loop

Abstract:
In this paper, we present three different methods we have developed for the design of an electrical impedance analyser implemented on an FPGA board. We describe in the first part the general principle of the methods : Ratiometric Measurement, Feedback Voltage Control and Adaptive Parametric Modelisation. In order to test and to compare the performances of each approach, the Hardware In the Loop strategy has been used. We present the steps from the mixed simulation using Matlab DSP Builder, which leads to the FPGA implementation. We investigate the limits and advantages for each method. The impedance analysis results of a model of an audio piezo transducer (7 kHz) are presented. The amplitude accuracy is less than 3 % and the analysis duration from 5 kHz to 10 kHz is about 54.5 ms for the first two methods.

Pages: 29 to 33

Copyright: Copyright (c) IARIA, 2011

Publication date: August 21, 2011

Published in: conference

ISSN: 2308-426X

ISBN: 978-1-61208-150-2

Location: Nice/Saint Laurent du Var, France

Dates: from August 21, 2011 to August 27, 2011