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A Novel High Speed Differential Ultra Low-Voltage CMOS Flip-Flop for High Speed Applications

Authors:
Yngvar Berg

Keywords: CMOS, low-voltage, Flip-Flop, High-Speed, Floating-Gate

Abstract:
In this paper we present a simple ultra low-voltage and high speed D flip-flop. The Flip-Flop may be used in any standard digital low-voltage CMOS applications. Furthermore, the ultra low-voltage Flip-Flop offers reduced data to output delay compared to conventional CMOS Flip-Flops. Different master latch configurations are presented and a differential symmetric ultra low-voltage Flip-Flop is presented. Simulated data using HSpice and process parameters for 90nm CMOS are provided. Preliminary results show that the proposed Flip- Flop has a delay less than 20% compared to a conventional CMOS Flip-Flop.

Pages: 11 to 16

Copyright: Copyright (c) IARIA, 2012

Publication date: August 19, 2012

Published in: conference

ISSN: 2308-426X

ISBN: 978-1-61208-213-4

Location: Rome, Italy

Dates: from August 19, 2012 to August 24, 2012