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ASIP for Multi-Standard Video Decoding

Authors:
Jae-Jin Lee
KyungJin Byun
NakWoong Eum

Keywords: multimedia processor, application-specific instruction processor, video decoding

Abstract:
Multiple international video standards in the market have been developed successfully for many commercial products. Application-specific instruction processor is a new design methodology to develop optimized processor. This paper proposes a new application-specific instruction set processor based on 6-stage pipelined dual issue VLIW+SIMD architecture and compiler for multi-standard video decoding. The processor takes 130K in gate count at 125MHz in 130nm technology. Compared to the existing ARM processor, the proposed processor results in about 20% speed improvement as well as smaller hardware complexity.

Pages: 37 to 42

Copyright: Copyright (c) IARIA, 2012

Publication date: August 19, 2012

Published in: conference

ISSN: 2308-426X

ISBN: 978-1-61208-213-4

Location: Rome, Italy

Dates: from August 19, 2012 to August 24, 2012