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Robustness of the Ultra Low-Voltage Domino Gates CMOS

Authors:
Omid Mirmotahari
Yngvar Berg

Keywords: NP domino logic; ultra low voltage; floating-gate; CMOS, high-speed; clock drivers; 90 nm process.

Abstract:
In this paper, we elaborate on the dimensioning of the ultra low voltage gate with keeper. We compare the gate configuration to ULV5 and demonstrate the potential and weaknesses of the new gate configuration with the keeper.We also pinpoint the crucial signal paths (mainly regarding the clock drivers) while also providing an overview of the propagation through a chain of gates.

Pages: 7 to 12

Copyright: Copyright (c) IARIA, 2013

Publication date: August 25, 2013

Published in: conference

ISSN: 2308-426X

ISBN: 978-1-61208-302-5

Location: Barcelona, Spain

Dates: from August 25, 2013 to August 31, 2013