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Novel High Speed and Robust Ultra Low Voltage CMOS NP Domino Carry Gate

Authors:
Abdul Wahab Majeed
Halfdan Solberg Bechmann
Yngvar Berg

Keywords: ULV; Carry Gate; NP domino.

Abstract:
Abstract—In this paper, a novel design of an Ultra Low voltage Carry Gate shall be presented. The main objective is to target the robustness of the presented ciruits. We shall also imply as to what extent these circuits can be improved and what their benefits, compared to conventional topologies, are. The design presented, compared to a conventional CMOS carry gate, is area efficient and high speed. The relative delay of a ULV carry gate lies at less than 3% compared to conventional CMOS carry gate. The circuits are simulated using the TSMC 90nm process technology and all transistors are of the Low Threshold Voltage (lvt) type.

Pages: 1 to 6

Copyright: Copyright (c) IARIA, 2014

Publication date: November 16, 2014

Published in: conference

ISSN: 2308-426X

ISBN: 978-1-61208-379-7

Location: Lisbon, Portugal

Dates: from November 16, 2014 to November 20, 2014