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Scan-shift Power Reduction Based on Scan Partitioning and Q'-D Connection

Authors:
Tiebin Wu
Li Zhou
Hengzhu Liu

Keywords: scan partition; Q'-D connection; low power test; scan-shift power.

Abstract:
Excessive test power consumption is a great concern in modern VLSI testing. This paper presents an efficient scan-shift power reduction scheme based on scan chain partitioning and Q'-D connection. After partitioning the scan chains into several segments equally, selective Q'-D connection is introduced to reconfigure each segment, which only exploits the Q' output port of the scan flip-flop and no additional hardware or routing overhead will be introduced. Experimental results show that the proposal can achieve 3.43% scan-shift power reduction on average with the help of selective Q¯ -D reconnection after scan partitioning. Furthermore, the proposed scan-shift power reduction technique can be acceptable for Built-In Self-Test (BIST) and non-BIST scan-based testing architecture without affecting test application time, test fault coverage, performance and routing overhead of the circuit under test.

Pages: 21 to 25

Copyright: Copyright (c) IARIA, 2014

Publication date: November 16, 2014

Published in: conference

ISSN: 2308-426X

ISBN: 978-1-61208-379-7

Location: Lisbon, Portugal

Dates: from November 16, 2014 to November 20, 2014