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A Study of Transparent On-chip Instruction Cache for NV Microcontrollers

Authors:
Dahoo Kim
Itaru Hida
Eric Fukuda
Tetsuya Asai
Masato Motomura

Keywords: embedded system; micro-controller; instruction cache; non-volatile; low power design

Abstract:
Demands for low energy microcontrollers have been increasing in recent years. Since most microcontrollers achieve user-programmability by integrating non-volatile (NV) memories, such as flash memories for storing their programs, the large power consumption required in accessing an NV memory has become a major problem. This problem becomes even critical when lowering the power-supply voltage of NV microcontrollers to achieve power and energy reduction. In this paper, we try to solve this problem by introducing an instruction cache and thus reducing NV memory access frequency. Unlike general-purpose microprocessors, it is important for microcontrollers used for real time applications in embedded systems that the program execution time can be calculated accurately prior to its execution. Therefore, we introduce a "transparent" instruction cache, which does not change the existing NV microcontroller's cycle-level execution time, for reducing power and energy consumption, but not for improving the processing speed. We have conducted detailed microarchitecture design based on a major industrial microcontroller architecture, and studied, as a preliminary evaluaion, hit rates of several instruction cache configurations.

Pages: 26 to 29

Copyright: Copyright (c) IARIA, 2014

Publication date: November 16, 2014

Published in: conference

ISSN: 2308-426X

ISBN: 978-1-61208-379-7

Location: Lisbon, Portugal

Dates: from November 16, 2014 to November 20, 2014