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Improving the Performance of a SOM-Based FPGA-Placement-Algorithm Using SIMD-Hardware

Authors:
Timm Bostelmann
Sergei Sawitzki

Keywords: FPGA; netlist placement; GPU computing; paral- lelization; SIMD

Abstract:
Programmable circuits and nowadays especially field-programmable gate arrays (FPGAs) are widely applied in demanding signal processing applications. In a previous work, we have introduced a method to improve the results of the netlist-placement for FPGAs with a self-organizing map (SOM). However, the presented algorithm conveys a comparably high computational effort. Considering modern, agile hardware / software codesign approaches, a slow design automation process can act as a kind of show-stopper, because software compilation is already distinctly faster. Thus, in this conceptual work, we present and evaluate different approaches to exploit the inherent parallelism of the SOM to increase the computation-speed. These approaches are based on using the single instruction multiple data (SIMD) capabilities of the central processing unit (CPU) and the graphics processing unit (GPU) for vector operations. Furthermore, we present benchmark results of an optimized implementation, based on using the CPU's SIMD units and introduce a concept for a GPU-accelerated implementation as work in progress.

Pages: 13 to 15

Copyright: Copyright (c) IARIA, 2016

Publication date: July 24, 2016

Published in: conference

ISSN: 2308-426X

ISBN: 978-1-61208-496-1

Location: Nice, France

Dates: from July 24, 2016 to July 28, 2016