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A Dynamically Reconfigurable NoC for Double-Precision Floating-Point FFT on FPGAs

Authors:
Thanh Bui
Braden Phillips
Michael Liebelt

Keywords: Network-on-chip, partial reconfiguration, floating point, FFT, parallel architecture, FPGA.

Abstract:
This paper presents a dynamically partially reconfigurable network on chip (NoC) on a field-programmable gate array (FPGA) for double-precision floating-point Fast Fourier Transforms (FFTs). This is one of the first published examples of a practical system using a dynamically reconfigurable NoC that has been implemented in existing FPGA technology. Up to 16 parallel double-precision floating-point processing elements (PEs) can be implemented on the FPGA. Using dynamic partial reconfiguration, a user can change the number of running PEs to choose an optimal power-performance operating point. The design provides much better performance than i7-3.4GHz CPUs running Matlab and competitive performance with static-only FFT systems and the Xilinx FFT IP core, but it has the advantage of saving power and releasing hardware resources when maximum FFT performance is not required. With all 16 PEs running, the design can process an FFT of up to 131072 points and achieves its maximum throughput of of 33.5 FLOPs/cycle on a Xilinx Virtex-7 XC7VX485T FPGA.

Pages: 52 to 57

Copyright: Copyright (c) IARIA, 2016

Publication date: July 24, 2016

Published in: conference

ISSN: 2308-426X

ISBN: 978-1-61208-496-1

Location: Nice, France

Dates: from July 24, 2016 to July 28, 2016