Home // CENICS 2018, The Eleventh International Conference on Advances in Circuits, Electronics and Micro-electronics // View article
Ultra-Low-Voltage Dual-Rail NAND/NOR for High Speed Processing
Authors:
Ole Herman Schumacher Elgesem
Omid Mirmotahari
Yngvar Berg
Keywords: Ultra-Low-Voltage; high-speed; ULVDR; NAND; CVSL.
Abstract:
This paper expands Ultra-Low-Voltage Dual-Rail (ULVDR) technology to 2-input logic gates. While previous research has been focused on inverters, it is important to investigate and demonstrate the function and speed of ULVDR in bigger more complex circuits. ULVDR offers a significant speed increase over the more traditional Cascode Voltage Switch Logic (CVSL). Using the industry standard TSMC 90 nm CMOS process and a supply voltage of 300 mV, ULVDR NAND gates are more than 50 times faster than CVSL (chain evaluation delay).
Pages: 1 to 4
Copyright: Copyright (c) IARIA, 2018
Publication date: September 16, 2018
Published in: conference
ISSN: 2308-426X
ISBN: 978-1-61208-664-4
Location: Venice, Italy
Dates: from September 16, 2018 to September 20, 2018