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Improving the Gradient Descent Based FPGA-Placement Algorithm

Authors:
Tobias Thiemann
Timm Bostelmann
Sergei Sawitzki

Keywords: EDA; FPGA; placement; gradient descent.

Abstract:
In a previous paper of the authors, a gradient descent based Field-Programmable Gate Array (FPGA) placement algorithm was presented. It achieved similar results to the reference (based on simulated annealing) regarding the bounding-box quality, while being on average 3.8 times faster. However, the critical path was significantly longer. The paper concluded by pointing out several possible areas of improvement, which could lead to better quality of the placement results and/or further increases to placement speed. These different suggestions were evaluated, and the results applied to the algorithm. This paper explains the process and shows the final results of the improved algorithm. The improvements lead to the final version of the program being roughly 5.1 times as fast as the reference, while also improving the bounding box cost by 1.27%, as well as the timing of the critical path by 16%, when compared to the original version.

Pages: 12 to 24

Copyright: Copyright (c) IARIA, 2020

Publication date: November 21, 2020

Published in: conference

ISSN: 2308-426X

ISBN: 978-1-61208-823-5

Location: Valencia, Spain

Dates: from November 21, 2020 to November 25, 2020