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A Comparison of Verilog Synthesis Frontends

Authors:
Daniel Stokes
Georgiy Krylov
Jean-Philippe Legault
Panos Patros
Kenneth B. Kent

Keywords: Field Programmable Gate Arrays (FPGA); Com-puter Aided Design (CAD); Verilog

Abstract:
A crucial consideration in choosing a frontend synthesis tool is the quality of the synthesised result. This kind of benchmarking is critical to choosing a fit-for-purpose tool. However, to the best of the authors' knowledge, the only comparison of Odin~II, the front-end of Verilog-to-Routing, and another synthesis tool was focused primarily on Odin~II and Yosys' performance with respect to commercial counterparts in the Xilinx ISE tool. Further, such an evaluation is to improve confidence in research findings utilising these tools. The quality of results for a poorly optimised research tool may not reflect the performance of real-world applications, adding uncertainty to any findings and requiring extra work from the researcher to obtain valid results. We compare Odin~II and Yosys targeting the Xilinx Artix-7 architecture provided by SymbiFlow.

Pages: 1 to 6

Copyright: Copyright (c) IARIA, 2021

Publication date: November 14, 2021

Published in: conference

ISSN: 2308-426X

ISBN: 978-1-61208-921-8

Location: Athens, Greece

Dates: from November 14, 2021 to November 18, 2021