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High-Level Synthesis of Hardware Accelerators for Deconvolution Engines

Authors:
Cristian Sestito
Robert Stewart
Stefania Perri

Keywords: Hardware accelerators; High-Level Synthesis; Deconvolution; Multiply Accumulations; FPGAs

Abstract:
Convolutional and Deconvolutional Neural Networks are widespread in several modern computer vision applications, such as high-resolution imaging, object classification and generation, image segmentation and many others. While several efficient hardware architectures are known in literature to accelerate the convolution task, the design of accelerators for deconvolution is still an open problem. The few existing deconvolution engines are customized to exploit in the best possible way specific hardware resources, thus suffering from platform-dependency that certainly allows maximizing speed performances and power-resource efficiency, but, on the other hand makes these designs unsuitable for the high-level synthesis approach. This paper presents a deconvolution structure described in the C++ high-level language and then synthesized at the register-transfer level of abstraction. Results demonstrate that, when characterized within the Xilinx XC7VX980tffg1930-1 device, the described architecture can up-sample a 256×256 input image to the 1024×1024 resolution using less than 3000 LUTs, 1028 18Kb BRAMs and ~640 FFs. The reached 121 MHz running frequency guarantees a frame rate higher than 50 fps to be achieved.

Pages: 1 to 4

Copyright: Copyright (c) IARIA, 2022

Publication date: October 16, 2022

Published in: conference

ISSN: 2308-426X

ISBN: 978-1-68558-009-4

Location: Lisbon, Portugal

Dates: from October 16, 2022 to October 20, 2022