Home // CENICS 2022, The Fifteenth International Conference on Advances in Circuits, Electronics and Micro-electronics // View article

Processing Speed Impact of the Pipeline-Length on a Custom RISC-V CPU for FPGAs

Authors:
Julian Weihe
Timm Bostelmann
Sergei Sawitzki

Keywords: CPU; FPGA; RISC-V; Pipeline; CoreMark

Abstract:
To achieve a higher processing speed of a Central Processing Unit (CPU), a higher clock frequency can be used. Since the underlying circuit is limited by the switching and signal runtimes, pipeline stages are installed to divide the signal paths. Due to the piecewise processing in the stages, the evaluation of the instruction, which is necessary for the program flow, occurs too late. An example of this are jump instructions in which the target address is not determined until new instructions have already been read. As a result, instructions have to be discarded or the evaluation has to be delayed. This leads to a reduced processing speed and a dependency on the program code. This work shows the difference between a two- and a five-stage CPU with CoreMark. For this purpose, two simple Reduced Instruction Set Computer generation five (RISC-V) CPUs with the instruction set rv32i were compared. At the same clock frequency, the two-stage CPU processes 21.358% more instructions per time than the five-stage CPU, which is slowed down by the pipeline structure. However, a 69.851% higher clock frequency is possible with the five-stage CPU, which leads to a 39.969% higher CoreMark score.

Pages: 5 to 8

Copyright: Copyright (c) IARIA, 2022

Publication date: October 16, 2022

Published in: conference

ISSN: 2308-426X

ISBN: 978-1-68558-009-4

Location: Lisbon, Portugal

Dates: from October 16, 2022 to October 20, 2022