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A Flexible Bufferless H-ARQ Processor Based on Dataflow Scheduling

Authors:
Pierre-Henri Horrein
Christine Hennebert
Frédéric Pétrot

Keywords: H-ARQ; flexible radio; reconfigurable hardware

Abstract:
Flexible radio is a challenging way to implement communication standards. In theses standards, Hybrid ARQ (H-ARQ) is admitted as a usual error control protocol. H-ARQ is a cross-layer protocol, offering a number of different possible versions, with multiple instantiations running concurrently. In this context, designing a flexible H-ARQ component is a necessity. This paper presents an H-ARQ processor able to cope with the possible versions of the protocol and any number of instantiations. Based on a modified hardware/software partitioning, it is able to dynamically reconfigure its operation mode. Data representation is used to create codewords, associated to an operation. A new buffer management scheme, based on software buffers and independent of the number of protocol instantiations, is proposed. The resulting architecture is able to process any H-ARQ protocol with no throughput penalty, in MIMO or SISO environments, and to support concurrent standards.

Pages: 48 to 53

Copyright: Copyright (c) IARIA, 2011

Publication date: April 17, 2011

Published in: conference

ISSN: 2308-4251

ISBN: 978-1-61208-131-1

Location: Budapest, Hungary

Dates: from April 17, 2011 to April 22, 2011