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Towards Virtual Fault-based Attacks for Security Validation

Authors:
Regis Leveugle
Mohamed Ben Jrad
Paolo Maistri

Keywords: security, dependability, design time robustness evaluation, SRAM-based FPGAs, ASICs

Abstract:
Applications increasingly rely on secure embedded systems or "trusted hardware". ASICs (or smart cards) are typically used for high security but SRAM-based FPGAs are also appealing to implement lower-cost and flexible systems. In both cases, designers need a validation of the achieved level of security before they undergo long and costly official security qualification. This paper presents a methodology to accurately evaluate at design time the robustness level with respect to fault-based attacks, without resorting to costly equipments. Practical results are shown. The same methodology can be used in other contexts, for example to evaluate the robustness with respect to particle hits and radiations in spatial or aeronautics electronics although in this case, error models are in general easier to handle.

Pages: 1 to 6

Copyright: Copyright (c) IARIA, 2011

Publication date: August 21, 2011

Published in: conference

ISSN: 2308-4324

ISBN: 978-1-61208-149-6

Location: Nice/Saint Laurent du Var, France

Dates: from August 21, 2011 to August 27, 2011