Home // DEPEND 2016, The Ninth International Conference on Dependability // View article

Static Worst-Case Execution Time Analysis Tool Development for Embedded Systems Software

Authors:
Thomas Jerabek
Martin Horauer

Keywords: architecture description language, instruction set simulator, worst-case execution time analysis

Abstract:
Analyzing the worst-case execution time of embedded systems software is useful for assessing parameters like schedulability, performance (especially with regard to deadlines), etc. A commonly accepted approach to obtain these values is by way of static analysis that uses the software along with a model of the target processors architecture. This paper describes the required steps to construct a tool to assess the worst-case execution time of a given application with the help of an opensource framework. The ensuing evaluation provides a comparison of the results with other approaches. In addition, this paper can be used as guide to implement an instruction set architecture of a target processor in order to enable various static analyses with the aim to estimate the worst-case execution time.

Pages: 7 to 14

Copyright: Copyright (c) IARIA, 2016

Publication date: July 24, 2016

Published in: conference

ISSN: 2308-4324

ISBN: 978-1-61208-492-3

Location: Nice, France

Dates: from July 24, 2016 to July 28, 2016