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The Impact of the Floorplan of Functional Units on 3D Multi-core Processors

Authors:
Hyung Gyu Jeon
Hong Jun Choi
Jong Myon Kim
Cheol Hong Kim

Keywords: Multi-core processor; 3D architecture; Temperature; Floorplan schemes

Abstract:
Interconnection delay is one of the most critical constraints in improving the performance of multi-core processors. In order to reduce the interconnection delay in the multi-core processor, 3D integration technology has been applied in designing multi-core processors. The 3D multi-core processor is composed of vertically stacked cores which are connected by through-silicon vias, leading to improved interconnection and power efficiency by reducing the physical wire length significantly. However, 3D multi-core processors have severe temperature problems caused by higher power density compared to 2D Multi-core processors. In this paper, we propose the thermal-aware floorplan schemes to solve the thermal problems in 3D multi-core processors by changing the location of functional units. According to our experimental results, the proposed floorplan schemes reduce the peak temperature by 12ºC on average with 3% performance gain.

Pages: 13 to 18

Copyright: Copyright (c) IARIA, 2012

Publication date: September 23, 2012

Published in: conference

ISSN: 2326-9383

ISBN: 978-1-61208-239-4

Location: Barcelona, Spain

Dates: from September 23, 2012 to September 28, 2012