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Hardware Accelerator for Low-Latency Privacy Preserving Mechanism

Authors:
Junichi Sawada
Hiroaki Nishi

Keywords: hardware; reconfigurable device; privacy-preserving data publishing.

Abstract:
With the recent growth in the quantity and value of data, data holders have come to realize the importance of being able to utilize information that is otherwise abandoned or concealed. In this situation, they face the difficulty of publishing data without revealing private information. Two of the methods used to protect private information when publishing data are privacy-preserving methods based on constraints known as k- anonymity and l-diversity. These methods enable the utilization of published data while preserving privacy, but incur a large computational cost. We solve this problem using a hardware architecture composed of Ternary Content Addressable Memory (TCAM), which can significantly accelerate the privacy preservation process. k-anonymity and l-diversity have not been studied in any significant way for efficient hardware implementation. Thus, this will be the first of its kind. An evaluation proves that an implementation of the proposed architecture on a reconfigurable device performs approximately 10-50 times faster than a RAM-based architecture.

Pages: 1 to 6

Copyright: Copyright (c) IARIA, 2012

Publication date: July 22, 2012

Published in: conference

ISSN: 2308-3735

ISBN: 978-1-61208-217-2

Location: Nice, France

Dates: from July 22, 2012 to July 27, 2012