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A Novel Realization of Sequential Reversible Building Blocks

Authors:
Vishal Pareek
Shubham Gupta
Sushil Chandra Jain

Keywords: reversible computing; sequential circuit; flip-flops; quantum computation

Abstract:
With phenomenal growth of high speed and complex computing applications, the design of low power and high speed logic circuits have created tremendous interest. Reversible computing has emerged as a solution for future computing. A number of combinational circuits have been developed but the growth of sequential circuits was not significant due to feedback and fan-out was not allowed. However allowing feedback in space, sequential logic blocks have been reported in literature. The target technology is likely on quantum computing devices. Reversible flip-flops are the most significant and basic memory elements that will be the target building block of memory for the forthcoming quantum computing devices. This paper proposes a novel reversible gate and its quantum realization. The design of reversible flip-flops, Serial In Parallel Out (SIPO) shift register and shift counter is shown by using our proposed gate and basic reversible gates. The proposed design of sequential reversible circuits has significant improvement over earlier designs in terms of quantum cost and hardware complexity. It is expected that it will enhance the growth of sequential reversible circuit. The proposed gate is also parity preserving gate. This characteristic of the gate may also be useful in fault tolerant sequential circuit design.

Pages: 1 to 6

Copyright: Copyright (c) IARIA, 2014

Publication date: May 25, 2014

Published in: conference

ISSN: 2308-3735

ISBN: 978-1-61208-339-1

Location: Venice, Italy

Dates: from May 25, 2014 to May 29, 2014