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Ternary Arithmetic Pipeline Architectures Using Multi-bit Memristors

Authors:
Dietmar Fey

Keywords: Memrisitve computing; Ternary logic; Signed-digit arithmetic

Abstract:
The paper addresses the possibilities exploiting the multi-bit storing features of memristor cells for balanced ternary signed-digit (SD) arithmetic pipelines realising addition, subtraction and multiplication. Different pipeline schemes using memristors as pipeline registers are shown in overview. Their functionality was verified on digital level by SystemC simulations and their performance is comparatively evaluated using analytic methods. In a ternary SD number system the digits of the operands can be assigned not only to 0 and 1 but also to minus 1. Such an SD representation has the great advantage that additions and subtractions can be carried out in $O(1)$ step, i.e., the run time is independent from the word length $N$. However, this requires a physical memory cell that allows to store reliably not only two but at least three states and in addition such a device has to offer fast access times and must be compatible with CMOS logic. All these constraints are fulfilled by memristors. Using memristor based pipeline registers offers different alternatives for implement fast arithmetic architecture circuits that differ from conventional ones. In particular, they allow to use more homogeneous pipelines for realising addition, subtraction and multiplication than current superscalar pipelines, which use for different operations also different pipeline paths. However, for the realisation of a homogeneous pipeline using memristors there are different possibilities. Those were evaluated in this paper concerning latency and hardware effort measured in number of required logic elements for computing and memristors for storing.

Pages: 1 to 6

Copyright: Copyright (c) IARIA, 2015

Publication date: March 22, 2015

Published in: conference

ISSN: 2308-3735

ISBN: 978-1-61208-389-6

Location: Nice, France

Dates: from March 22, 2015 to March 27, 2015