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Supporting the Neon and VFP Instruction Sets in an LLVM-based Binary Translator

Authors:
Yu-Chuan Guo
Wuu Yang
Jiunn-Yeu Chen
Jenq-Kuen Lee

Keywords: binary translation; cloud computing; LLVM; floating-point instruction; Neon, VFP; vector instruction; virtualization.

Abstract:
Binary translation attempts to emulate one instruction set with another on the same or different platforms. This important technique is widely used in instruction-setarchitecture migration, binary instrucmentation, dynamic optimizations, software security, and fast arhitecture simulation. Vector and floating-point instructions are widely used in many applications, including multimedia, graphics, and gaming. Though these instructions are usually simulated with software in a binary translator, it is important to support them in such a way that the host SIMD (single instruction multiple data) and floatingpoint hardware is efficiently used in the translation process. We report our design and implementation of the emulation of ARM Neon and VFP (vector floating point emulation) instructions in the MC2LLVM (machine-to-low-level-virtual-machine) binary translator. Our approach can take full advantage of the vector and floating-point functional units, if present, of the host machine. The experimental results show that code generated by MC2LLVM with the Neon and VFP extensions achieves an average speedup of 1.174x in SPEC 2006 benchmark suites compared to code generated by MC2LLVM without the Neon and VFP extensions.

Pages: 104 to 109

Copyright: Copyright (c) IARIA, 2015

Publication date: May 24, 2015

Published in: conference

ISSN: 2308-3913

ISBN: 978-1-61208-405-3

Location: Rome, Italy

Dates: from May 24, 2015 to May 29, 2015