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Template Based Automatic Generation of Runsets

Authors:
Elena Ravve

Keywords: Design Rule Manuscript; Design Rule Checker Runset; Layout versus Schematic Runset; Test Cases; Templates; Automatic Generation.

Abstract:
Layout of modern electronic devices consists of billions of polygons for chemical layers. There exist hundreds of design rules, defining how the polygons may be drowning. Design rule checkers (DRC) guarantee that the chip may be manufactured. Moreover, any manufacturing process allows a finite set of supported legal devices. Layout versus schematic (LVS) comparison determines one-to-one equivalency between a circuit schematic and its layout. The correctness of the DRC and LVS runsets are verified using test cases, which contain shapes, representing failing and passing conditions. Creation and maintenance of the complete set of runsets and the corresponding test cases is complicated and time consuming process that should be automatized. Usually almost all design rules may be divided into a set of categories: width, space/distance, enclosure, extension, coverage, etc. Moreover, the set of legal devices for any process may be divided into a set of technology independent categories: transistors, capacitors, resistors, diodes and so on. In this paper, we use these categories in order to define re-usable patterns. The integrator will use the pre-defined patterns in order to compose the design rule manuscript (DRM) rather than to write it. DRC and LVS runsets are then automatically generated using the DRM. Moreover, we use the patterns in order to automatically create the corresponding test cases.

Pages: 54 to 60

Copyright: Copyright (c) IARIA, 2016

Publication date: November 13, 2016

Published in: conference

ISSN: 2308-4529

ISBN: 978-1-61208-513-5

Location: Barcelona, Spain

Dates: from November 13, 2016 to November 17, 2016