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A Survey of Power-Aware Network-on-Chip Design Techniques

Authors:
Emmanuel Ofori-Attah
Michael Opoku Agyeman

Keywords: Network-On-Chip; Power Consumption; ManyCore; Routers.

Abstract:
The Network-on-Chip paradigm has been herald as the solution to the communication limitation that System-onChip poses. As we usher into the billion-transistor era, Networkon-Chip which was once deemed as the solution is defecting due to its power demanding components. Several techniques have been proposed over the years to improve the performance of the Network-on-Chip, trading off power efficiency. However, low power design solution is one of the essential requirements of future Network-on-Chip based System-on-Chip applications. Power dissipation can be reduced by efficient routers, architecture saving techniques and communication links. This paper presents recent contributions and efficient saving techniques at the router, Network-on-Chip architecture and Communication link level.

Pages: 25 to 30

Copyright: Copyright (c) IARIA, 2018

Publication date: June 24, 2018

Published in: conference

ISSN: 2308-4529

ISBN: 978-1-61208-641-5

Location: Venice, Italy

Dates: from June 24, 2018 to June 28, 2018