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Fault Tolerant Distributed Embedded Architecture and Verification

Authors:
Chandrasekaran Subramaniam
Prasanna Vetrivel
Srinath Badri
Sriram Badri

Keywords: Distributed architecture; Fault tolerance; Security module; Model verification; Assertion technique.

Abstract:
The objective of the work is to propose a distributed embedded architecture model for tolerating faults while performing security functions using multiple field programmable gate arrays (FPGA). The hardware encryption and decryption modules are used as customized modules within the devices to act as a cooperative system to tolerate omission and commission faults. The different security functions are communicating through a common UART channel and security operations are synchronized with standard protocols initiated by an embedded micro controller. The decision in locating the working and available modules among a pool of devices is carried out by the microcontroller using an intelligent F-map mechanism and directs the control instructions. The model is scalable with increased number of similar devices when connected across the common communication channel. The model is verified for all its paths using Symbolic Model Verifier, NuSMV to assert the dynamic behavior of the architecture in case of different faulty conditions.

Pages: 146 to 152

Copyright: Copyright (c) IARIA, 2012

Publication date: January 30, 2012

Published in: conference

ISSN: 2308-3956

ISBN: 978-1-61208-176-2

Location: Valencia, Spain

Dates: from January 30, 2012 to February 4, 2012