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Optimization of Sparse Matrix Arithmetic Operations and Performance Improvement using FPGA

Authors:
Dinesh Kumar Murthy
Semih Aslan

Keywords: Sparse matrix; latency; throughput; memory; FPGA; hardware architecture.

Abstract:
The increasing importance of sparse connectivity representing real-world data has been exemplified by recent work in the areas of graph analytics, machine language, and high-performance computing. Sparse matrices are the critical component in many scientific computing applications, where increasing sparse operation efficiency can contribute significantly to improving overall system efficiency. The main challenge lies in efficiently handling the nonzero values by storing them using a specific storage format and then performing matrix operations, taking advantage of the sparsity. This paper proposes an optimized algorithm for performing sparse matrix operations in storage and hardware implementation on Field-Programmable Gate Arrays (FPGAs). The results are obtained from implementing the sparse algorithm on hardware for matrices of different sizes. Sparsity percentages and sparsity patterns achieved low latency and high throughput compared with the standard algorithm. Further, the number of resources utilized was primarily reduced, enabling the FPGAs to focus on larger, more interesting problems.

Pages: 1 to 5

Copyright: Copyright (c) IARIA, 2021

Publication date: April 18, 2021

Published in: conference

ISSN: 2308-3964

ISBN: 978-1-61208-835-8

Location: Porto, Portugal

Dates: from April 18, 2021 to April 22, 2021