Home // ICN 2012, The Eleventh International Conference on Networks // View article

CTC Turbo Decoding Architecture for LTE Systems Implemented on FPGA

Authors:
Cristian Anghel
Valentin Stanciu
Cristian Stanciu
Constantin Paleologu

Keywords: turbo codes; Max Log MAP decoder; FPGA implementation; LTE standard

Abstract:
This paper describes a turbo decoder for Long Term Evolution (LTE) standard, release 8, using a Max Log MAP algorithm. The Forward Error Correction (FEC) block dimensions, as indicated in the standard, are inside a range of 40 to 6144 bits. The coding rate is 1/3, the puncturing block not being taken into discussion here. The number of turbo iterations is variable, but in this study it was usually set to 3. The turbo decoder is implemented on a Xilinx Virtex-5 XC5VFX70T Field Programmable Gate Array (FPGA).

Pages: 199 to 204

Copyright: Copyright (c) IARIA, 2012

Publication date: February 29, 2012

Published in: conference

ISSN: 2308-4413

ISBN: 978-1-61208-183-0

Location: Saint Gilles, Reunion

Dates: from February 29, 2012 to March 5, 2012