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On the FPGA Implementation of the VR-RLS Algorithms

Authors:
Cristian Anghel
Silviu Ciochina

Keywords: VR-RLS; FPGA; efficient implementation; adaptive algorithms

Abstract:
This paper presents the main elements proposed for an efficient implementation on Field Programmable Gate Array (FPGA) of our novel Variable-Regularized Recursive Least Squares (VR-RLS) algorithm. The followed performance axes are the overall processing speed and the amount of used hardware resources. We also focus on this adaptive algorithm performance in the scenario of acoustic echo cancellation (AEC), from the finite precision implementation degradation point of view.

Pages: 98 to 101

Copyright: Copyright (c) IARIA, 2017

Publication date: April 23, 2017

Published in: conference

ISSN: 2308-4413

ISBN: 978-1-61208-546-3

Location: Venice, Italy

Dates: from April 23, 2017 to April 27, 2017