Home // ICONS 2014, The Ninth International Conference on Systems // View article

Efficient FPGA-Based Architecture for Spike Sorting Using Generalized Hebbian Algorithm

Authors:
Wen-Jyi Hwang
Chi-En Ke
Sheng-Ying Lai
Jung-Gen Wu

Keywords: Spike Sorting; FPGA; Generalized Hebbian

Abstract:
An efficient VLSI architecture for fast spike sorting is presented in this paper. The architecture is able to perform feature extraction based on the Generalized Hebbian Algorithm (GHA). The employment of GHA allows efficient computation of principal components for subsequent clustering and classification operations. The hardware implementation of GHA features high throughput and high classification success rate. The proposed architecture is implemented by Field Programmable Gate Array (FPGA). It is embedded in a System-On-Programmable-Chip (SOPC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design with high speed computation for spike trains corrupted by large noises.

Pages: 6 to 11

Copyright: Copyright (c) IARIA, 2014

Publication date: February 23, 2014

Published in: conference

ISSN: 2308-4243

ISBN: 978-1-61208-319-3

Location: Nice, France

Dates: from February 23, 2014 to February 27, 2014