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PACER: Peripheral Activity Completion Estimation and Recognition

Authors:
Daniel Moore
Alexander Dean

Keywords: embedded systems; energy aware embedded computing; embedded profiling; embedded performance analysis; Dynamic Voltage Scaling (DVS); low-power; low-energy; wireless sensor node (WSN); adaptive embedded systems

Abstract:
Embedded peripheral devices such as memories, sensors and communications interfaces are used to perform a function external to a host microcontroller. The device manufacturer typically specifies worst-case current consumption and latency estimates for each of these peripheral actions. Peripheral Activity Completion, Estimation and Recognition (PACER) is introduced as a suite of algorithms that can be applied to detect completed peripheral operations in real-time. By detecting activity completion, PACER enables the host to exploit slack between the worst-case estimate and the actual response time. These methods were tested independently and in conjunction with IODVS on multiple common peripheral devices. For the peripheral devices under test, the test fixture confirmed decreases in energy expenditures of up to 80% and latency reductions of up to 67%.

Pages: 38 to 45

Copyright: Copyright (c) IARIA, 2018

Publication date: April 22, 2018

Published in: conference

ISSN: 2308-4243

ISBN: 978-1-61208-626-2

Location: Athens, Greece

Dates: from April 22, 2018 to April 26, 2018