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Cellular Automata-based Wear Leveling in Resistive Memory

Authors:
Sutapa Sarkar

Keywords: Resistive memory, Spatial access characteristics, Wear leveling, Density classification task, Periodic Boundary Cellular Automata.

Abstract:
Due to spatial locality of reference, repetitive writes cause stress to few contiguous cache memory blocks. If the underlying technology is resistive memory, those blocks suffer with endurance problem and wear out at much faster rate than NAND/NOR Flash memories (10^5 to 10^6 program/erase cycles). In CMPs cache memory, uneven distribution of writes and/or malicious attacks cause system failures due to repetitive writes on a particular memory block. To avoid wear out of memory cells at premature stage, writes are distributed through wear leveling schemes. This work reports an efficient scheme of wear leveling in resistive memory using the concept of Cellular Automata (CA). Probably this is a unique effort of wear leveling, using Von Neuman’s concept of cellular automata, that targets to make uniform writes throughout all memory blocks with spatial access pattern predictions. The contiguous write-stressed memory blocks are defined as a zone subjected to remapping. Two stage hierarchical Periodic Boundary Cellular Automata (PBCA) is used to perform Density Classification Task (DCT) to select the cache zone (remapping candidates). Thereafter, identified memory blocks are remapped to new addresses by an algebraic technique. This access aware write management policy can be worked along with fault tolerant design for implementation of a robust memory subsystem.

Pages: 32 to 38

Copyright: Copyright (c) IARIA, 2019

Publication date: March 24, 2019

Published in: conference

ISSN: 2308-4243

ISBN: 978-1-61208-696-5

Location: Valencia, Spain

Dates: from March 24, 2019 to March 28, 2019