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Scalable Embedded Architecture for High-speed Video Transmissions and Processing

Authors:
Jiri Halak
Sven Ubik
Petr Zejdl

Keywords: HD-SDI, video, FPGA, network communication, high-speed

Abstract:
In this paper, we present a scalable and extendable hardware architecture for processing and transfer of ultra-high-definition video over high-speed 10/40/100~Gbit networks with very low latency. We implemented this architecture in a single FPGA device. Data processing is divided between FPGA resources and an embedded operating system. The FPGA resources can be moved between various processing functions depending on the device mode. The resulting inexpensive and compact device is intended for high quality video transfers and processing with a low latency and to support deployment in education and remote venues.

Pages: 161 to 166

Copyright: Copyright (c) IARIA, 2011

Publication date: October 23, 2011

Published in: conference

ISSN: 2163-9027

ISBN: 978-1-61208-166-3

Location: Barcelona, Spain

Dates: from October 23, 2011 to October 29, 2011