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1 Gbps Ethernet TCP/IP and UDP/IP Header Compression in FPGA

Authors:
Milan Stohanzl
Marek Bobula
Zbynek Fedra

Keywords: Field Programable Gate Array (FPGA); Ethernet; header; compression; connection; IP; TCP; UDP.

Abstract:
This paper presents a study about the hardware implementation of the TCP/IP and UDP/IP headers compression for the point-to-point communication. The implementation is focused on the achievement of minimum latency and high compression ratio. The applied compression technique is a dictionary-based method. For the TCP/IP, the fixed length of the compressed header was implemented. On the contrary, the variable length of the compressed header was implemented for the UDP/IP. The dictionaries are filled from the original data on both sides. No additional transmissions are used for retaining the continuity of the dictionary content.

Pages: 136 to 142

Copyright: Copyright (c) IARIA, 2012

Publication date: November 18, 2012

Published in: conference

ISSN: 2163-9027

ISBN: 978-1-61208-231-8

Location: Lisbon, Portugal

Dates: from November 18, 2012 to November 23, 2012