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3D On-chip Data Center Networks Using Circuit Switches and Packet Switches

Authors:
Takahide Ikeda
Yuichi Ohsita
Masayuki Murata

Keywords: network on chip; data center; energy consumption; delay; 3D on-chip network

Abstract:
The energy consumption of the data center becomes a great problem. One approach to reduce the energy consumption of the data center is to use {sl on-chip data centers}, which are integrated circuit chips that perform the tasks in a data center. On-chip data centers are constructed of cores and the network between cores. Because the tasks in the data center are performed by the cooperation between servers, the network between cores in the on-chip data center may have a large impact on the performance of the chip. In this paper, we investigate the network structures for the on-chip data centers. We focus on the 3Dnetwork using both circuit and packet switches, and compare the energy consumption and the delay of the candidate network structures. The results show that (1) the servers should connect to the packet switches in the same layer, (2) the packet switches should connect to the circuit switches in all layers, and (3) the layer including both of circuit switches and packet switches should be avoided to reduce the energy consumption and the delay.

Pages: 125 to 130

Copyright: Copyright (c) IARIA, 2013

Publication date: October 27, 2013

Published in: conference

ISSN: 2163-9027

ISBN: 978-1-61208-305-6

Location: Venice, Italy

Dates: from October 27, 2013 to October 31, 2013