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Performance of Low Buffer Resource Flexible Router for NoCs

Authors:
Israel Mendonça dos Santos
Felipe M.G. França
Victor Goulart

Keywords: Flexible Routers, Network-on-Chip (NoC), Adaptive Router, Buffer Resources

Abstract:
Nowadays, the performance of advanced multi-core systems is mostly limited by communication bottlenecks instead of computing speed or memory resources. Interconnection networks start to replace buses as the standard system-level interconnection infrastructure. Many researchers have been working on on-chip interconnection networks (Network-on-Chip - NoC) to improve its performance in terms of latency, throughput and power consumption. Buffers are the most influential element affecting performance in this architecture, and also the most expensive resource. The vast range of applications concurrently executing in the network and their different communication patterns leave some buffers of the routers underutilized. In this paper, we study the performance of low buffer resource flexible routers which can adaptively schedule resources (buffers) according to the dynamic behavior of the communication demand in the NoC. Our simulations showed this router architecture was able to improve throughput up to 21% or have similar performance while using half the number of buffers compared to a standard router.

Pages: 35 to 41

Copyright: Copyright (c) IARIA, 2014

Publication date: October 12, 2014

Published in: conference

ISSN: 2163-9027

ISBN: 978-1-61208-368-1

Location: Nice, France

Dates: from October 12, 2014 to October 16, 2014