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Using Embedded FPGA for Cache Locking in Real-Time Systems

Authors:
Antonio Martí Campoy
Francisco Rodríguez-Ballester
Rafael Ors Carot

Keywords: Real-Time Systems; Locking Caches; FPGA.

Abstract:
In recent years, locking caches have appeared as a solution to ease the schedulability analysis of real-time systems using cache memories maintaining, at the same time, similar performance improvements than regular cache memories. New devices for the embedded market couple a processor and a programmable logic device designed to enhance system flexibility and increase the possibilities of customisation in the field. This arrangement may help to improve the use of locking caches in real-time systems. This work propose the use of this embedded programmable logic device to implement a logic function that provides the locking cache controller the information it needs in order to determine if a referenced main memory block has to be loaded and locked into the cache; we have called this circuit a Locking State Generator.

Pages: 26 to 30

Copyright: Copyright (c) IARIA, 2012

Publication date: October 21, 2012

Published in: conference

ISSN: 2308-3484

ISBN: 978-1-61208-226-4

Location: Venice, Italy

Dates: from October 21, 2012 to October 26, 2012