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A Parallel Hardware Architecture for Fork-Join Parallel Applications

Authors:
Atakan Dogan
Ismail San
Kemal Ebcioglu

Keywords: Parallel applications; parallel hardware; hardware thread; caches; NoCs

Abstract:
In order to facilitate the implementation on hardware and improve the performance of a class of fork-join applications that can be modeled by an OpenMP program, a parallel hardware architecture with a specialized memory hierarchy is proposed. Furthermore, three different case studies are provided to show how this model can be employed for the hardware acceleration of such applications.

Pages: 57 to 59

Copyright: Copyright (c) IARIA, 2018

Publication date: July 22, 2018

Published in: conference

ISSN: 2308-3484

ISBN: 978-1-61208-655-2

Location: Barcelona, Spain

Dates: from July 22, 2018 to July 26, 2018