Home // INTENSIVE 2013, The Fifth International Conference on Resource Intensive Applications and Services // View article
Authors:
Mark Westmijze
Marco J. G. Bekooij
Gerard J. M. Smit
Keywords: cache, bandwidth, real-time, control, jitter
Abstract:
Systems with chip multi-processors are currently used for several applications that have real-time requirements. In chip multi-processor architectures, many hardware resources such as parts of the cache hierarchy are shared between cores and by using such resources, applications can significantly interfere with each other. In previous work, we showed that a single X-ray imaging streaming applications can be executed with low jitter on such systems. However, it was assumed that only one application would be running on the system, which prevents system integration where multiple real-time and best- effort applications are executing on a single chip multi-processor. In this paper, we address the limited bandwidth in the cache hierarchy, which can cause threads to interfere with each other significantly. We propose a technique that implements cache bandwidth reservation in software, by dynamically duty-cycling best-effort applications, based on their cache bandwidth usages using processor performance counters in order to control the influence of best-effort applications on real-time applications. With this technique we can control the latency increase of real- time applications that is caused by best-effort application in order to satisfy real-time requirements with a minimal reduction in best-effort performance. The results of the experiments with real- life applications indicate that we can control the increase of the latency to such an extent that we can almost completely eliminate the influence of bandwidth sharing in the cache at the cost of best-effort performance.
Pages: 1 to 7
Copyright: Copyright (c) IARIA, 2013
Publication date: March 24, 2013
Published in: conference
ISBN: 978-1-61208-258-5
Location: Lisbon, Portugal
Dates: from March 24, 2013 to March 29, 2013