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H.264 Parallel Optimization on Graphics Processors

Authors:
Elias Baaklini
Hassan Sbeity
Smail Niar

Keywords: Multimedia; H.264/AVC decoder; Video Compression; Optimization; Parallel Computing; Graphics Processors

Abstract:
Multimedia applications are present in most mobile hand-held devices. The H.264 standard is currently dominating the video compression world. H.264 has high computational complexity requiring large amount of processing resources. Many techniques emerged that optimize H.264 using parallelization on multicore systems ranging from groups of pictures until the smallest block of pixels. We propose a parallelization technique based on rows of macroblocks with a light dependency detection algorithm that optimizes data parallelization and minimizes dependency synchronization stall time. The parallel H.264 implementation is tested on 2, 4, 8, and 16 cores processors using CIF and HD video resolutions benchmarks. The experimental results show that, in terms of execution time and parallel scalability, CIF video sequences peak at 4 cores with a speedup of 3.1 and HD video sequences peak at 8 cores with a speedup of 6.2. The H.264 parallel implementation is then tested on a graphics processor simulator of the Evergreen family of AMD GPUs reaching a speedup up to 12.1 times without communications overhead. Our results shall aid to find the best parallel configuration of the H.264 standard with the most suitable multicore platform to use in terms of time complexity and parallel efficiency.

Pages: 109 to 114

Copyright: Copyright (c) IARIA, 2013

Publication date: April 21, 2013

Published in: conference

ISSN: 2308-4448

ISBN: 978-1-61208-265-3

Location: Venice, Italy

Dates: from April 21, 2013 to April 26, 2013