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Amplifying Side Channel Leakage by Hardware Modification of Xilinx Zynq-7 FPGA Evaluation Boards

Authors:
Nadir Khan
Sven Nitzsche
Raffaela Frank
Lars Bauer
Jörg Henkel
Jürgen Becker

Keywords: FPGA; Side Channel Attack; Test Vector Leakage Assessment; Advanced Encryption Standard; Power Analysis

Abstract:
The Aim of this work is to enhance the side channel information that is revealed by the power consumption of a Field Programmable Gate Array (FPGA). An initial measurement setup is proposed for measuring the signal quality, and then adjustments and modifications to the hardware are done to enhance this quality. Once an acceptable signal is measurable, data is gathered and useful information in this raw data is determined using a standard leakage assessment methodology. The used methodology generates a quantitative score regarding the presence of useful information in the raw data, and can therefore indicate whether a system is vulnerable to side channel attacks or not. In this work, several modifications are presented along with their effect on the captured signal’s quality and the amount of useful information in the collected raw data.

Pages: 53 to 59

Copyright: Copyright (c) IARIA, 2019

Publication date: October 27, 2019

Published in: conference

ISSN: 2162-2116

ISBN: 978-1-61208-746-7

Location: Nice, France

Dates: from October 27, 2019 to October 31, 2019