Home // SENSORCOMM 2015, The Ninth International Conference on Sensor Technologies and Applications // View article

Design Methodology of TDC on Low Cost FPGA Targets

Authors:
Foudil Dadouche
Thimothé Turko
Wilfried Uhring
Imane Malass
Jérémy Bartringer
Jean-Pierre Le Normand

Keywords: Time-to-Digital Converter; FPGA; Chip Planner; Carry Chain Logic

Abstract:
This work aims to introduce a design methodology of Time-to-Digital Converters (TDCs) on low cost Field-Programmable Gate Array (FPGA) targets. First, the paper illustrates how to take advantage of the presence of carry chains in elementary logic elements of the FPGA in order to enhance the TDC resolution. Then, it describes how to use the Chip Planner tool to place the partitions composing the system in user specified physical regions. This allows the placement of TDC partitions so that the routing paths are constrained. As a result, the user controls the propagation delay effectively through the connection network. The paper ends by applying the presented methodology to a case study showing the design and implementation of high resolution TDC dedicated to fast imaging systems. The obtained resolution of 42 ps using a low cost FPGA target Cyclone family is very promising and suitable for a large amount of fast applications.

Pages: 29 to 34

Copyright: Copyright (c) IARIA, 2015

Publication date: August 23, 2015

Published in: conference

ISSN: 2308-4405

ISBN: 978-1-61208-425-1

Location: Venice, Italy

Dates: from August 23, 2015 to August 28, 2015