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FPGA-aware Transformations of LLVM-IR

Authors:
Franz Richter-Gottfried
Sebastian Hain
Dietmar Fey

Keywords: OpenCL; LLVM; high-level synthesis; FPGA; if- conversion; bitwidth reduction

Abstract:
The paper presents hardware-aware optimizations of the assembly language used by LLVM to optimize resource usage when an algorithm written in the Open Computing Language (OpenCL) is translated into a design for a field programmable gate array (FPGA) by the tool OCLAcc. In signal processing, latency and throughput of a solution are important, but also its efficiency. FPGAs offers high performance and low energy consumption for many applications, at the cost of a complex development. With high-level synthesis (HLS) the design process can be simplified significantly. We introduce our transformation of the control flow and how we minimize the bitwidth of data and operations performed. In contrast to existing work, we focus on the applicability for FPGAs and HLS from OpenCL. Both optimizations allow the generation of simpler hardware. We present metrics to rate the results with estimations of FPGA resources needed and demonstrate them using the Sobel operator, which is part of many image processing applications. Our results show that we can completely eliminate branches and reduce the total amount of bits by 16 % for a typical input configuration.

Pages: 15 to 20

Copyright: Copyright (c) IARIA, 2016

Publication date: June 26, 2016

Published in: conference

ISSN: 2519-8432

ISBN: 978-1-61208-487-9

Location: Lisbon, Portugal

Dates: from June 26, 2016 to June 30, 2016