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A Matlab/Simulink Simulation Approach for Early Field-Programmable Gate Array Hardware Evaluation

Authors:
Celso Barbante
Jose Oliveira

Keywords: Model verification; Matlab; FPGA design

Abstract:
This paper presents a Matlab test bench development for Field-Programmable Gate Array hardware simulation. When a design uses hardware blocks provided by third-part vendors (known as Integration Packages - IP), several options can be set in the block configuration page, inside vendor tool, and affect how the block behaves. These configuration options should be evaluated for any integration package one may be interested in and the test bench proposed facilitates the evaluation of any block-specific configuration parameters, enabling a three times reduction of block configuration time.

Pages: 89 to 93

Copyright: Copyright (c) IARIA, 2013

Publication date: October 27, 2013

Published in: conference

ISSN: 2308-4537

ISBN: 978-1-61208-308-7

Location: Venice, Italy

Dates: from October 27, 2013 to October 31, 2013